1. Field of the Invention
The present invention relates to a semiconductor IC (Integrated Circuit) having a pass transistor logic circuit. More particularly, the present invention relates to a semiconductor IC with an improved production yield and a reduced cost.
2. Description of the Related Art
In recent years, there have been growing demands for reducing power consumption, increasing an operating speed and reducing a chip area of a semiconductor IC. In order to meet such demands, "White paper on low power consumption LSIs", pp.98-104, Nikkei Business Publications Inc., for example, has proposed a circuit configuration using a pass transistor logic.
In the pass transistor logic circuit proposed in this publication, a logic circuit is formed by NMOS transistors, whereby transmission of a low level signal is desirable. However, a voltage level of a high level signal being output is reduced by a threshold value of the NMOS transistor due to a substrate effect.
In view of this, other conventional pass transistor logic circuits have been proposed, as will be described below, which employ various measures to pull up the reduced high level signal (which has been reduced by the threshold value of the NMOS transistor) to the desired high level. This is done to obtain a sufficient driving capacity for a subsequent-stage circuit.
A CPL (Complementary Pass-Transistor Logic) proposed by Hitachi Ltd. has been proposed with a CMOS inverter at an output section for restoring a blunted high logic level to its original level, and a PMOS cross-coupled latch for suppressing a static current of the CMOS inverter, thereby augmenting the driving force for a subsequent-stage load. For more details, see "K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, and A. Shimizu, "A 3.8 ns CMOS 16.times.16-b Multiplier Using Complementary Pass-Transistor Logic", IEEE J. Solid-State Circuits., Vol. 25, No. 2, pp. 388-395 (1990)".
Another conventional example is an SRPL (Swing Restored Pass-Transistor Logic) proposed by Toshiba Corporation, which uses a CMOS latch for ensuring that the output reaches the desired level. For more details, see "A. Parameswar, H. Hara and T. Sakurai, "A high Speed, Low Power, Swing Restored Pass-Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications", Proc. IEEE 1994 CICC, pp. 278-281, May 1994.
In these conventional pass transistor logic circuits, a CMOS buffer is provided for every predetermined number of serially-connected transistors for restoring a signal level.
Thus, conventionally, in order to reduce power consumption, increase an operating speed and reduce a chip area of an LSI using a pass transistor logic circuit in place of a CMOS logic circuit, a PMOS transistor is necessary for driving a high level signal.
However, a PMOS transistor has an operating speed which is about 1/3+L of that of an NMOS transistor due to the carrier mobility difference therebetween. This spoils the characteristic of a pass transistor logic circuit being faster than a CMOS logic circuit.
Conventionally, in order to increase the operating speed of the PMOS transistor to a level comparable to that of an NMOS transistor, it is necessary to provide a PMOS transistor which is larger than an NMOS transistor. However, this makes it difficult to reduce the chip area.
In addition, since a logic circuit in the pass transistor logic circuit is formed by NMOS transistors, the relative size of the NMOS transistor region with respect to the PMOS transistor region is often larger as compared with that of a CMOS logic circuit. Therefore, with a layout method conventionally used in a CMOS process, some area is likely to be wasted in a P well. As a result, the chip area for a certain number of transistors is likely to be larger than that in the conventional CMOS logic circuit.
For the two reasons set forth above, it has been difficult to reduce the chip area in a semiconductor IC using the conventional pass transistor logic circuit.